The present invention is directed to integrated circuits and, more particularly, to measuring signal skew for an asynchronous flash memory controller.
System designs demand more and more non-volatile memories, either with high density and very high writing throughput for data storage applications or with fast random access for code execution. The flexibility and low cost of flash memory makes it a frequently utilized, well-consolidated and mature technology for most non-volatile memory applications. Electronic devices such as mobile phones, tablets, networking devices, etc. commonly incorporate a processor and flash memory. Typically the processor uses external flash memory, whether or not some flash memory is also included in the processor, since embedded memories can be costly in terms of price and power consumption. Such a processor desirably has an integrated flash memory controller (IFC) that can manage various types of flash memory, such as NAND flash (SLC and MLC), NOR flash, EPROM, and SRAM, where address and data are shared on a bus.
An IFC provides programming and signal interfaces, similar to an enhanced local bus controller, for external flash memory. An asynchronous IFC provides an interface for asynchronous flash memory devices but does not provide a reference clock with the output data signals of the flash memory device.
The specifications for a IFC include restrictions on the skew between multi-bit data and control output signals from the controller, that is to say the variation in the delays of output signals relative to the corresponding input signals. Compliance of products with specifications, including the IFC skew specifications, is checked using automatic test equipment (ATE). Typically an ATE checking skew specifications uses edge searching to measure when a signal edge occurs relative to the test pattern signal, or to a clock signal. In edge searching, the output signal is repeatedly probed (sampled) and compared with the expected result at moments that are later and later in the test cycle until the output signal becomes equal to, or becomes different from, the expected result. Conventional methods of measuring the skew rely on an interface clock. In the absence of such a clock, in the case of a controller for asynchronous flash memory devices, conventional methods involve (n−1) edge searches for n signals and nC2 measurements, where nC2 is the number of combinations of n signals taken two at a time. The resulting testing rapidly becomes complex and the test times long. For example, in a device that has a sixteen-bit wide data bus and seven control signals, such a conventional method of measuring the skew would involve twenty-two searches for signals and two hundred and fifty-three data measurements.
Accordingly, it would be advantageous to have a method of measuring signal skew for asynchronous flash memory controllers efficiently with a short test time.